Video module

Video module keeps information to be displayed in its buffer memory, converts this information into RGB bitmap components, and drives VGA signals to generate an image on a screen.

node 717 node 617 node 517 node 716 node 616 node 516 node 715 node 615 node 515 node 415 node 315 node 714 node 614 node 514 node 414 node 314 node 713 node 613 node 513 node 413 node 313 node 712 node 612 node 512 node 412 node 312 node 711 node 611 node 411 node 311 node 710 node 709 video module floorplan

Video module is another autonomous part of the system. It is responsible for generating an image on a VGA screen. It starts running when the Clock module begins generating clock signal. The video module is composed of several subunits.

Video buffer is implemented in nodes 313, 314, 315, and 415. Each node reserves 47 words of RAM for data, except for node 415 (last buffer node) where 59 words of RAM are available. This makes 200 words in total, starting at address 0 in node 313 and ending at address 199 in node 415. Access to the block buffer memory is possible from RIGHT port of node 313. Out of reset, the block buffer memory is filled with this intro screen.

intro screen

Block buffer memory is accessed on two occasions; when video controller reads data to be displayed on a screen, and when editor needs to load new content into the buffer or to store the current buffer content into external SRAM. Nodes 311 and 312 form an interface that allows data to pass to and from the block buffer memory.

In addition to that node 311 reserves 16 words as another character buffer. This buffer is used to implement a command line and also an indicator of the block being displayed. Video module controller reads data from this buffer when displaying the bottom line of the screen.

Activity of video module nodes is synchronized with a 12 MHz signal distributed from the Clock module via node 416. The signal enters into node 516, where clock and sync signal generator block begins. The signal continues to node 517, which generates HSYNC signal, then it goes to node 617, where VSYNC signal is generated, and via nodes 616 and 615 into node 715 generating 500 ns character clock pulses. Those are distributed to shared pin 17 of analog nodes 709, 713, and 717 via intra-chip connections. Clock signal path within the video module is shown in the scheme below.

video clock path

The video controller itself begins in node 411. It builds a whole frame by requesting symbols from memory in a sequential manner, and sending those symbols downstream. It controls what memory (block buffer or command line) is read from. It also checks for end-of-line and end-of-block symbols, and signals downstream when those symbols are encountered. Knowing that each row is composed of twenty scan lines it sends content of each row twenty times.

From node 411 the data flow through node 412, where tokens are expanded into strings of characters. Strings for all 48 tokens are stored in nodes 413 and 414. A stream of tags and characters continues to node 512, where tags are replaced by spaces, and color information from a tag is combined with each character that follows. This node also keeps information about current cursor position, and displays it when appropriate. Next node 513 generates pixel bitmap slices for each character displayed. It keeps track of current display line, and reads a corresponding bitmap slice from nodes 514 and 515. Slices with color codes are distributed by wire nodes 613, 612, 611, 711, 614, 714, and 715 to color tables in nodes 710, 712, and 716. Finally, bitmap slices and color component values are sent to analog nodes 709, 713, and 717, where they are converted with DACs to voltages on RGB lines.